Instruction-set Design Issues: what does the ML instruction format(s)

1) Which instructions to include:

looks for a substring within a string

2) Which built-in data types

3) Instruction format:

4) # registers

5) Addressing modes supported

0 Address

(Stack machine)

1 Address

(Accumulator machine)

2 Address 3 Address
PUSH M LOAD M MOVE (X Y) MOVE (X Y)
POP M STORE M    
ADD ADD M ADD (X X + Y) ADD (X Y + Z)
SUB SUB M ADD (X X - Y) SUB (X Y - Z)
MUL MUL M MUL (X X * Y) MUL (X Y * Z)
DIV DIV M DIV (X X / Y) DIV (X Y / Z)

R = A + B * C

0 Address

(Stack machine)

1 Address

(Accumulator machine)

2 Address 3 Address
PUSH B

PUSH C

MUL

PUSH A

ADD

POP R

LOAD B

MUL C

ADD A

STORE R

MOVE R, B

MUL R, C

ADD R, A

MUL R, B, C

ADD R, R, A

Load/Store Architecture - operands for arithmetic operations must be from/to registers

LOAD R1, B

LOAD R2, C

MUL R3, R1, R2

LOAD R4, A

ADD R3, R4, R3

STORE R3, R

Addressing Modes

How can labels for subprogram names, local variables, and global variables be represented in the executable machine language?

direct/absolute addressing - the memory address of where the label resides is put into the machine language instruction (EA, effective address = direct)

e.g., assume subPgm2 is at 40016, and global x is at 800016

How relocatable is the code in memory if direct addressing is used?

How many bits are needed to represent a direct address?

Other addressing modes:

Immediate - part of the ML instruction contains the value

Register - operand is contained in a register

Register Indirect - operand is pointed at by an address in a register

Indirect - operand is pointed at by an address in a memory

Displacement - operand is pointed at by an address in a register plus offset

a) Base-register addressing

Often the reference register is the stack pointer register to manipulate the run-time stack.

b) Relative/PC-relative - base-register addressing where the PC is the implicitly referenced register

c) Indexing - ML instruction contains a memory address and a register containing an index

Useful for array access.

Reduced Instruction Set Computers (RISC)

Two approaches to instruction set design:

1) CISC (Complex Instruction Set Computer) e.g., VAX

1960's: Make assembly language (AL) as much like high-level language (HLL) as possible to reduce the "semantic gap" between AL and HLL

Alleged Reasons:

Characteristics of CISC:

Problems with CISC:

2) RISC (1980's) Addresses these problems to improve speed.

(Table 14.1 - characteristics of some CISC and RISC processors)

General Characteristics of RISC:

RISC Instruction-Set Architecture (ISA) can be effectively pipelined