0) In Figure 5.2 (synchronous read), how was bus skew handled?

1) In Figure 5.3, which device (CPU or Memory) is driving the control wires:

a) I0/?

b) / write?

c) ?

2) Draw a Memory write operation with two wait states.

3) In Figure 5.7 (asynchronous read), how was bus skew handled?

4) How does a hierarchy of buses as shown in Figure 5.14 improve performance of a computer system?

5) What is the purpose of the "Bridge"s as shown in Figure 5.14?