• 16 registers numbered from 0 to 15
• each register has 32-bits
• two write ports
• three read ports

a) What how many bits(/"wires") would be need for each of the following?

• data to be written for a write port
• specifying the register number of a read port
• specifying the register number of a write port
• output read from a read port

b) How many write enable wires would be needed for the whole register file?

c) How many decoders would be needed in the implementation of the whole register file? Explain how you arrived at that number and specify the type of decoders (i.e., number of inputs and number of outputs for each decoder)

d) How many multiplexers would be needed in the implementation of the whole register file? Explain how you arrived at that number and specify the type of multiplexers.

2. Suppose we have a 32 word memory.

a) How many bits would be needed for the binary address?

b) What would be the range of binary addresses?

c) If we wanted to group four words together into a block and number the block starting at zero (i.e., block 0 consists of addresses 0, 1, 2, 3; block 1 consists of addresses 4, 5, 6, 7, etc.), then what would be similar about the (binary) addresses of all the words within the same block?

3. Consider the 4 x 3 memory in Figure 16.1 (page 668). If we scaled up this design to 4 M x 4 (2 ²² words of 4-bits each), then:

a) How many total gates would be needed to implement the decoders?

b) How many total gates would be needed to implement the MUXs?

c) Assuming 5 gates per bit of memory, compare the number of gates needed to store the memory values with the number of gates need for overhead (gates for the decoder and MUX(s))?