Implementation of Large Memory Chips

Consider a 4M x 4-bit chip which has a 22-bit addresses since 4M = 222.

Logically/Externally, we view a 4M x 4-bit memory as pictured below with:

When we want to read a word, we supply a 22-bit address, and receive the corresponding 4-bit word.

The register-file implementation (see handout), does not scale well for large memories for several reasons:

These problems are solved by

To help us see how the 4M x 4-bit memory gets mapped to the 2048 x 2048 x 4 memory array on the next page consider splitting memory into 2048 word blocks as shown below.

Each bit of a word is split into a separate 2048 x 2048 square memory "array". Each of these square memory arrays is 2048 x 2048 = 211 x 211 = 222 = 4M bits.

The 22-bit address of the 4M memory is split into two 11-bit parts. The upper 11-bits is first used to activate the correct row within the square memory arrays. Of the 2048-bit row that is read from each memory array, we are interested in only one bit. The lower 11-bits of the address specifies the location of the desired bit within the 2048-bit row.