Implementing Large Memory with Smaller Chips

Consider for example, implementing 4M x 32 bits memory with 256KB x 1 bit chips.

The 256KB x 1 chips are implemented as square arrays of 512 x 512.

We will use an two-dimensional array of the 256KB x 1 chips to implement the larger memory.

The number of chips per row would be 32 bits / 1 bit = 32 chips.

The number of chips per column would be 4M / 256K = 222 / 218 = 24 = 16 chips per column.

The 22-bit address of the 4M x 32 bit memory would be split up as follows: